(1) Field of the Invention
The present invention relates to the field of power consumption control within an electronic device. More specifically the present invention relates to a method and apparatus for power control within a microprocessor architecture.
(2) Prior Art
With the emergence of the portable computer market (such as laptop, hand-held and pen-based computer systems), there is a desire and strong need for a new personal computer that operates at a very low power consumption. Although recently the personal computer market has been attempting to move to power supply voltages of 3 volts, instead of 5 volts, a substantial focus of reducing power consumption within a computer system concentrates on reducing power consumption to chips and component blocks that are in a state of little or no activity. Ideally, when a chip or component is not currently active or when it is anticipated that such chip or component will not be used in the near future, it would be beneficial to reduce its power consumption, and thereby operate the electronics at a lower power consumption rate than when the chip is constantly drawing power. One method of achieving low power consumption in electron devices ("chips") is to employ power management circuits. Power management circuits put the chip or component into a state that draws little or no current, even though the supply voltage remains coupled to the chip. This state is known as a power down state. Power management circuits are particularly advantageous to utilize when a chip is not currently active or during temporary periods when it is anticipated that a chip or chip component will not be needed.
One type of prior art power management circuit utilizes external counters to detect activity in the chip. These counters are usually timers keyed to the last access of the chip. These timers, sometimes called "watchdog" timers, act as retriggerable one-shots, such that when no chip activity occurs for a predetermined period of time, the chip is allowed to power down. One problem with such a power management scheme is that external control of the power management circuit (i.e., via the counter) is required. When external counters signal that the chip may be put into the powered down state, or mode, an external switch turns off the power. Hence, actually entering the power down mode is externally controlled. Furthermore, these power management circuits are not transparent to software controlling the chip. Also, these power management circuits, including the extra timer function, may become rather complex and consume extra power themselves. It would be advantageous to provide a power consumption system that was not overly complex and also transparent to a user. The present invention provides such results.
Another method of powering down circuit components is to use external chip circuitry, i.e., circuitry outside the chip. In order to put a chip into the power down mode using external circuitry, the clocks must be stopped. In order to stop the clocks or at least gate a clock, a bus cycle must be launched or a process must be physically executed at the bus cycle level. The absence of any bus cycles being executed (e.g., through default) is an indication that the device can be shut off. Once a bus cycle did occur to a device that was powered off, a mechanism is required for the clock to start. Also, the device would require a means of recovering fast enough to respond to the cycle. Alternatively, if an access to the powered down device occurred, the processor might have to execute an instruction twice so that a powered down device would have time to respond. Although these prior art mechanisms may provide a viable alternative design, they are very complicated.
Portable computer systems place a high premium on reducing power consumption. The primary mechanism to reduce the active power consumption is to reduce the number of transitions of internal logic, essentially dividing or stopping the clock. This is the case because in modern computer electronic design, power is consumed when logic gates change state and charge is passed from Vcc to Vss. Stop the clock transition within a circuit component and the logic gates of that component will cease changing states. On some computer chips, such as a microprocessor chip, there are numerous functional units and buffers. Each functional unit and buffer unit is responsible for performing a different function. At any given time, some of the functional units may be idle and not performing their designated functions, while others are performing their functions. Unnecessary clocking of unused functional units and buffer units of a processor may contribute to excessive power consumption. For instance, in a processor having a separate floating point unit, when the floating point unit is not executing any floating point instructions, the clocking to the floating point unit causes power to continue to be consumed. It would be beneficial to provide a power consumption system that could selectively disable a functional unit of a microprocessor. The present invention provides such capability.
One functional unit within a microprocessor is the Translation Lookaside Buffer (TLB) unit which is a part of the paging unit of the microprocessor. The TLB performs translation of memory addresses within the microprocessor for various remapping of program and data code executed by the microprocessor. Within the x86 architecture (such as 80286, 80386, and 80486 microprocessors) and DOS applications the TLB may not be required. Further, not all instructions require use of the TLB to perform address translations. This could be the case because some instructions do not require memory accessing at all. However, in prior art system designs, whether or not the TLB is disabled or needed, the TLB unit continues to operate to generate translation information. When the unit is disabled or not needed, this information generated by the TLB unit is simply ignored by the microprocessor. It would be beneficial, then, to provide a system to temporarily disable the actual operation of the Translation Lookaside Buffer unit when such unit is disabled or when instructions do not require address translation by the TLB. Powering down of the TLB would then help to reduce the overall power consumption of the microprocessor. The present invention offers such advantageous capability. Further, it would be beneficial to provide a system that powers up the TLB unit when it is desired for use. The present invention provides such functionality.
Accordingly, it is an object of the present invention to provide a mechanism that allows on-chip functional units to be automatically stopped when not being used and automatically restarted when it is detected that use is anticipated. It is a further object of the present invention to provide a power management system operating within a microprocessor for powering down a Translation Lookaside Buffer unit when the TLB unit is disabled or not needed. It is further an object of the present invention to provide a system to provide power to the TLB unit when the TLB unit is not disabled and when it is anticipated that the TLB unit will be used. It is further an object of the present invention to power down and power up the TLB unit of the microprocessor by selectively interrupting the clock supply signal to the TLB unit. These and other objects of the present invention will become clear upon review of the discussions of the preferred embodiment of the present invention to follow.